The present disclosure relates to layouts of semiconductor memory devices.
Among semiconductor memory devices, read only memories (ROMs) have an important function as nonvolatile memories, i.e., the function of not erasing data even after turning-off of power sources, and are widely used for various semiconductor products. A memory cell of a ROM can store 1-bit data by a single transistor, and thus, is more advantageous in terms of circuit scale, i.e., the area, than an SRAM which needs multiple transistors to store 1-bit data, for example.
In microfabrication processes, pattern formation has a large number of variation factors, and even target patterns having the same shape are greatly affected by other patterns disposed near the target patterns. In particular, memory cells are susceptible to characteristic variations. This is because the memory cells themselves are made of fine patterns, and in addition, a peripheral pattern greatly differs between a center portion and an end portion of a memory array in which a large number of the same type of memory cells are arranged in a wide range.
According to a conventional technique, in a ROM in which stored data is implemented by the difference among the threshold voltages of memory cell transistors, the amount of an impurity to be implanted immediately under the gate is controlled during fabrication in order to control the threshold voltage. In addition, at the interface between an actual use region and a blank region outside the actual use region, in order to reduce the influence of the blank region on a peripheral part of the actual use region, dummy processing for reducing variations depending on whether a resist opening is present or not is performed on a resist in the blank region. In this manner, characteristics of the actual use region is stabilized (see Japanese Patent Publication No. 2002-158297).
On the other hand, a contact control ROM in which data is stored depending on whether contact is present or not is also known. According to a conventional technique, in a contact control ROM, n-channel memory cell transistors in memory cells which are located adjacent to each other along the bit lines are separated from each other by a dummy transistor which is held OFF. In this manner, stress applied to the memory cell transistors is reduced (see Japanese Patent Publication No. 2004-327574).